Low-dropout (LDO) regulators are DC linear voltage regulator (i.e., devices used to maintain a constant output voltage) configured to operate with a very small input-output differential voltage. The advantages of LDO regulators include low minimum operating voltage, high-efficiency operation and low heat dissipation.
As schematically illustrated in FIG. 1, the main components of an LDO regulator 100 are (A) a power field effect transistor (FET) 110 connected between an input line 120 (VIN) and an output line 130 (VOUT), and (B) a differential amplifier (error amplifier) 140. The power FET 110 is a transistor that uses an electric field to control the shape and, hence, the conductivity of a channel of one type of charge carrier (n for electrons and p for holes) in a semiconductor material. In other words, conductivity across the power FET's source and drain terminals is variable, depending on a signal applied on a gate terminal of the power FET. The FET transistors may have a metal-oxide-semiconductor (MOS) structure.
One input of the differential amplifier 140 receives feedback which is a fraction of the output, and another input of the differential amplifier 140 receives a stable voltage reference (known as “bandgap reference”) (VREF). If the output voltage (VOUT) rises too high relative to the reference voltage (VREF), the signal applied to the gate terminal of the power FET 110 changes to maintain a constant output voltage (VOUT).
LDO regulators are used in many devices. For example, sources including LDO regulators configured as integrated circuits (IC) can be found in wireless devices such as mobile terminal systems (e.g., cell phones, smartphones, etc.), digital media players (e.g., MP3s and MP4s), DVD players, portable PCs, tablets, etc. Since these devices are often in a “standby” state to reduce power usage and prolong device battery life, it is advantageous to be able to operate these sources in low-power mode (LPM) in addition to their regular manner of operation in high-power mode (HPM). An example would be sources including LDO regulators, such as those used in smartphones, where they provide several mA of output current and consume a few hundred μA in HPM. In LPM, it is desirable for the source to maintain the output voltage for a lower source load, while the source's current (power) consumption is as low as possible (i.e., significantly lower than HPM).
FIG. 2 illustrates a layout of a conventional source 200 including an LDO regulator. The source input 210 and the source output 220 are arranged on the same side (bottom in FIG. 2) and the control loop 240 of the LDO regulator (which includes the differential amplifier) is arranged on the opposite side (upper side in FIG. 2). The LDO regulator's power transistor 230 occupies a middle portion. Input and output lines may extend from the source input 210 and the source output 220 over the power MOS transistor 230.
Two possible approaches for providing LPM are described below, but these have not necessarily been previously conceived or pursued. Therefore, unless otherwise indicated, these approaches are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
A first approach is de-biasing the LDO circuit providing HPM. As suggested in FIG. 1, some components of the LDO regulator 100 (indicated by dashed arrows converging to the “LPM” label) are varied to have different values in LPM than in HPM. The varied components are the current mirror 150, the sampling resistor 160, resistor 170 and differential amplifier 180 (used as a buffer, having gain 1 and low output impedance), etc. This approach is optimized in terms of circuit area reusing the LDO regulator, but has some inherent drawbacks. For instance, the approach is not flexible, and requires major modifications to replace the fixed elements with variable elements and to provide mechanisms for switching between HPM and LPM. Additionally, power consumption in LPM remains significant. A de-biased LDO still has the same structure in LPM as in HPM, and so usually includes several gain stages and a buffering stage resulting in relatively high LPM current (power) consumption.
A second approach employs a dedicated circuit (independent from the LDO regulator used for HPM) to provide LPM. This LPM-dedicated circuit is active in LPM, while being inactive (stopped, turned OFF) in HPM. To manage the LPM/HPM transitions, this solution requires a specific digital control based on delays to create overlapping phases. However, this second approach is also not very flexible because the digital control (in particular, the delays) has to be adapted specifically for each LDO regulator. Additionally, the LPM/HPM transitions managed by the digital control are usually spiky, rather than smooth.
Accordingly, it would be desirable to provide an LPM solution for sources including LDO regulators that avoids the afore-described problems and drawbacks.